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TDA7468D
TWO BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR WITH BASS ALC SURROUND
1
FEATURES
INPUT MULTIPLEXER - 4 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT BASS ALC TREBLE AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: - TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS EXTERNALLY ADJUSTABLE SURROUND
Figure 1. Package
SO28

Table 1. Order Codes
Part Number TDA7468D TDA7468D13TR Package SO28 Tape & Reel
applications in Hi-Fi systems. Selectable input gain is provided. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained

2
DESCRIPTION
The TDA7468D is a volume tone (bass and treble) balance (Left/Right) processor for quality audio Figure 2. PIN CONNECTION (Top view)
VS MIC IN1_L IN2_L IN3_L IN4_L MUX_L IS_L TREBLE_L BASSI_L BASSO_L OUT_L DGND SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D99AU1057
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND CREF IN1_R IN2_R IN3_R IN4_R MUX_R IS_R TREBLE_R BASSI_R BASSO_R OUT_R ALC SDA
June 2004
REV. 1 1/22
2/22
MUX-R IS-R TREBLE-R BASSI-R 20 50K gm non-inverting inverting + TREBLE BASS 0dB VARIABLE MIX 6dB 9dB 12dB 17 63dB att. /1dB step + 6dB gain -14 to +14dB /2dB step -14 to +14dB /2dB step -24 att. /8dB step OUT-R 19 18 BASSO-R 21 22 + BASS_ALC CONTROL 14 I2C BUS DECODER + LATCHES 15 13 HALF_WAVE RECTIFIER + SCL SDA DGND non-inverting inverting + 0dB 6dB 9dB 12dB VARIABLE MIX + 63dB att. /1dB step + 6dB gain 12 TREBLE -14 to +14dB /2dB step BASS -14 to +14dB /2dB step -24 att. /8dB step OUT-L gm 50K 7 MUX-L 8 IS-L 9 TREBLE-L 10 BASSI-L 11 BASSO-L 28 GND 27 CREF VREF SUPPLY 1 VS
IN-R4
23
TDA7468D
50K
IN-R3
24
INPUT SELECT
buffer gain: 0 to 14dB gain / 2dB step
50K
Figure 3. BLOCK DIAGRAM
IN-R2
25
50K
IN-R1
26
50K
MIC-MIX
2
50K
0dB, 6dB 10dB, 14dB
ALC
16
IN-L1
3
50K
IN-L2
4
INPUT SELECT
buffer gain: 0 to 14dB gain / 2dB step
50K
IN-L3
5
50K
IN-L4
6
50K
D99AU1058A
TDA7468D
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 0 to 70 -55 to 150 Unit V C C
Table 3. THERMAL DATA
Symbol Rth j-pin Parameter Thermal Resistance Junction-pins Value 85 Unit C/W
Table 4. QUICK REFERENCE DATA
Symbol VS VCL THD Supply Voltage Max. input signal handling Parameter Min. 5 2 0.01 % 0.1 100 90 0 -87 -14 -14 86 14 0 +14 +14 Typ. 9 Max. 10 Unit V Vrms % % dB dB dB dB dB dB dB
Total Harmonic Distortion VI = 1Vrms; f = 1KHz Total Harmonic Distortion VI = 0.1Vrms; f = 1KHz
S/N SC
Signal to Noise Ratio Vout = 1Vrms (0dB)
Channel Separation f = 1KHz Input Gain (2dB step) Volume Control (1dB step) Treble Control (2dB step) Bass Control (2dB step) Mute Attenuation
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TDA7468D
ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb = 25C, VS = 9V, f = 1KHz all controls flat (G = 0dB), unless otherwise specified)
Symbol SUPPLY VS IS SVR RIN Supply Voltage Supply Current Ripple Rejection Input Resistance Clipping Level Input Separation Minimum Input Gain Maximum Input Gain Step Resolution Input Resistance Mic Input Gain 1 Mic Input Gain 2 Mic Input Gain 3 Mic Input Gain 4 Mixing Rate Input Resistance Minimum Input Gain Maximum Input Gain Inverting Gain Minimum Mixing Rate Maximum Mixing Rate Crosstalk of Mux Output to 100% IS Buffer Gain 40 6 63 61 0.5 63 1 TBD 24 22 7 24 8 TBD 84 26 9 65 1.5 35 -1 35 THD = 0.3% 60 35 2 80 -1 5 9 9 90 50 2.5 100 0 14 2 50 14 10 6 0 50 50 0 12 -1 0 100 % % dB dB dB dB dB dB dB dB dB dB dB 65 1 65 1 65 10 V mA dB K Parameter Test Condition Min. Typ. Max. Unit
INPUT STAGE
VCL
SIN Ginmin Ginmax Gstep MIC RIN Gmic1 Gmic2 Gmic3 Gmin4 MIXmic Rin Ginmin Ginmax GinV Mixmin Mixmax Crosstal k Gbuffer
Vrms
dB dB dB dB K dB dB dB dB % K dB dB
SURROUND
VOLUME CONTROL CRANGE1 Vol 1 Control Range AVMAX1 ASTEP1 Match1 AVMAX2 ASTEP2 Match2 Vol 1 Max. Attenuation Vol 1 Step Resolution Matching Vol 2 Max. Attenuation Vol 2 Step Resolution Matching
CRANGE2 Vol 2 Control Range
AVMAX1+ Vol 1 + Vol 2 Max Attenuation AVMAX2
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TDA7468D
ELECTRICAL CHARACTERISTICS (continua) (refer to the test circuit Tamb = 25C, VS = 9V, f = 1KHz all controls flat (G = 0dB), unless otherwise specified)
Symbol BASS CONTROL Gb BSTEP RB Rattack1 Rattack2 Rattack3 Rattack4 Thresh1 Thresh2 Thresh3 Thresh4 Gt TSTEP Rt VOCL RL VOUT ENO Control Range Step Resolution Internal Feedback Resistance Attack Time Resistor 1 Attack Time Resistor 2 Attack Time Resistor 3 Attack Time Resistor 4 Threshold 1 Threshold 2 Threshold 3 Threshold 4 Control Range Step Resolution Internal Resistance Clipping Level Output Load Resistance DC Voltage Level Output Noise BW = 20Hz to 20KHz; All gains 0dB; output muted flat S/N SC d Signal to Noise Ratio Channel Separation Left/Right Distortion AV = 0; VI = 0.1Vrms ; AV = 0; VI = 1Vrms ; SC Channel Separation left/right Total Tracking Error BUS INPUT VIL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage (ACK) VIN = 0.4V IO = 1.6mA 2.5 -5 0.4 5 0.8 1 V V A V 0.01 90 0 1 All gains 0dB; VO = 1Vrms ; 5 10 100 90 0.1 15 V V dB dB % % dB dB THD = 0.3% 2 2 4.5 Max. Boost/cut +13.0 1 Max. Boost/cut 12.0 1 33 14.0 2 44 12.5 25 50 100 700 485 320 170 +14.0 2 25 2.5 +15.0 3 16.0 3 55 dB dB K K K K K mVrms mVrms mVrms mVrms dB dB K Parameter Test Condition Min. Typ. Max. Unit
BASS ALC CONTROL
TREBLE CONTROL
AUDIO OUTPUTS
Vrms
K V
GENERAL
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6/22
5.6K 3.3nF 100nF 100nF MUX-R IS-R TREBLE-R 20 50K gm buffer gain: 0 to 14dB gain / 2dB step non-inverting inverting VARIABLE MIX + TREBLE BASS 0dB 6dB 9dB 12dB 17 -14 to +14dB /2dB step -14 to +14dB /2dB step -24 att. /8dB step OUT-R 63dB att. /1dB step + 6dB gain 19 18 BASSI-R BASSO-R 21 22 + BASS_ALC CONTROL 14 I2C BUS DECODER + LATCHES 15 13 HALF_WAVE RECTIFIER + SCL SDA DGND buffer gain: 0 to 14dB gain / 2dB step non-inverting inverting + 0dB 6dB 9dB 12dB VARIABLE MIX + 63dB att. /1dB step + 6dB gain 12 TREBLE -14 to +14dB /2dB step BASS -14 to +14dB /2dB step -24 att. /8dB step OUT-L gm 50K 7 MUX-L 8 IS-L 9 TREBLE-L 10 BASSI-L 11 BASSO-L 28 GND 27 CREF VREF SUPPLY 1 VS 10F
TDA7468D
0.47F
IN-R4
23
50K
Figure 4. TEST CIRCUIT
0.47F
IN-R3
24
INPUT SELECT
50K
0.47F
IN-R2
25
50K
0.47F
IN-R1
26
50K
0.47F MIC-MIX
2
50K
0dB, 6dB 10dB, 14dB
0.47F
ALC
16
1M
0.47F
IN-L1
3
50K
0.47F
IN-L2
4
INPUT SELECT
50K
0.47F
IN-L3
5
50K
0.47F
IN-L4
6
50K
D99AU1059A
TDA7468D
3
APPLICATION SUGGESTIONS
The first and the last stages are volume control blocks. The control range is 0 to -63dB (mute) with 1dB step resolution for this first one, 0 to 24dB (mute) with 8dB step resolution for the last one. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7468D audioprocessor provides 2 bands tones control. 3.1 Bass, Stages The Bass cell has an internal resistor Ri = 44K typical. Several filter types can be implemented, connecting external components to the Bass IN and OUT pins. The fig.5 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed as follows: 1 F C = ----------------------------------------------------------------2 R1 R2 C 1 C2 R2 C2 + R2 C1 + R i C1 A V = --------------------------------------------------------------R 2 C1 + R2 C2 R 1 R2 C1 C 2 Q = ------------------------------------------------R2 C1 + R2 C2 Viceversa, once FC, AV, and Ri internal value are fixed, the external components values will be: AV - 1 C1 = ----------------------------------------2 FC Ri Q Q C1 C2 = ----------------------------2 AV - 1 - Q
2 2
AV - 1 - Q R2 = ---------------------------------------------------------------------2 C1 FC ( A V - 1 ) Q 3.2 Treble Stage The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25K typical) and an external capacitor connected between treble pins and ground. 3.3 CREF The suggested 10F reference capacitor (CREF) value can be reduced to 4.7F if the application requires faster power ON. Figure 5.
Ri internal IN C1 R2
D95AU313
OUT C2
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TDA7468D
4
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7468D and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 4.1 Data Validity As shown in fig. 6, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 4.2 Start and Stop Conditions As shown in fig.7 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 4.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 4.4 Acknowledge The master (P) puts a restive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 4). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 4.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 6. Data Validity on the I2CBUS
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 7. Timing Diagram of I2CBUS
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 8. Acknowledge on the I2CBUS
SCL 1 2 3 7 8 9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
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TDA7468D
5
SOFTWARE SPECIFICATION
Interface Protocol The interface protocol comprises:

A start condition (S) A chip address byte, containing the TDA7468D address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P)
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X B DATA SUBADDRESS LSB ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU420
ACK = Acknowledge S = Start; P = Stop A = Address B = Auto Increment
6
EXAMPLES
6.1 No Incremental Bus The TDA7468D receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 0 D3 D2 D1 D0 ACK MSB DATA DATA LSB ACK P
D96AU421
6.2 Incremental Bus The TDA7468D receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored. The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 1 D3 D2 D1 D0 ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU422
Table 5. POWER ON RESET CONDITION
MSB D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 LSB D0 0
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TDA7468D
7
DATA BYTES
Address = (HEX) 10001000. Table 6. FUNCTION SELECTION: First byte (subaddress)
MSB D7 X X X X X X X X D6 X X X X X X X X D5 X X X X X X X X D4 B B B B B B B B D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SUBADDRESS INPUT SELECT & MIC INPUT GAIN SURROUND VOLUME LEFT VOLUME RIGHT TREBLE & BASS OUTPUT BASS ALC
B = 1: INCREMENTAL BUS; ACTIVE B = 0: NO INCREMENTAL BUS X = INDIFFERENT 0/1
Table 7. INPUT SELECTION & MIC
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 0 0 0 1 1 1 0 0 1 0 1 D1 0 0 1 1 LSB D0 INPUT SELECT 0 1 0 1 IN1 IN2 IN3 IN4 MUTE (IN5) ON (IN5) OFF MIC Gain: 14dB Gain: 10dB Gain: 6dB Gain: 0dB OFF ON
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TDA7468D
Table 8. INPUT GAIN SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1
GAIN = 0 to 30dB
LSB D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1
INPUT GAIN 2dB STEPS 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB
Table 9. SURROUND
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 SURROUND MODE 1 0 ON OFF GAIN 0 0 1 1 0 1 0 1 0dB 6dB 9dB 12dB MIXING 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 inverting : 100% inverting :50% inverting : 25% 0% non-inverting : 100% non-inverting : 75% non-inverting : 50% mute BUFFER GAIN 1 0 0 6dB SURROUND
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TDA7468D
Table 10. VOLUME
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 VOLUME 1dB STEPS 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB 8dB STEPS 0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB VOLUME 2 0dB -8dB -16dB -24dB
VOLUME = 0 to-87dB
Table 11. VOLUME setting 1
Target Volume (dB) 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15 Volume1 1dB step (dB) 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 -8 0 Volume1 8dB step (dB) 0 Volume2 8dB step (dB) 0
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TDA7468D
Table 11. VOLUME setting 1 (continua)
Target Volume (dB) -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39 -40 -41 -42 -43 -44 -45 -46 -47 -48 -49 -50 -51 -52 -53 -54 -55 Target Volume (dB) -56 -57 Volume1 1dB step (dB) 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 Volume1 1dB step (dB) 0 -1 Volume1 8dB step (dB) -56 Volume2 8dB step (dB) 0 -48 0 -40 0 -32 0 -24 0 Volume1 8dB step (dB) -16 Volume2 8dB step (dB) 0
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TDA7468D
Table 11. VOLUME setting 1 (continua)
-58 -59 -60 -61 -62 -63 -64 -65 -66 -67 -68 -69 -70 -71 -72 -73 -74 -75 -76 -77 -78 -79 -80 -81 -82 -83 -84 -85 -86 -87 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 -56 -24 -56 -16 -56 8
Table 12. VOLUME setting 2
Target Volume (dB) 0 -1 -2 -3 -4 -5 -6 -7 Volume1 1dB step (dB) 0 -1 -2 -3 -4 -5 -6 -7 Volume1 8dB step (dB) 0 Volume2 8dB step (dB) 0
14/22
TDA7468D
Table 12. VOLUME setting 2 (continua)
Target Volume (dB) -8 -9 -10 -11 -12 -13 -14 -15 -16 -17 -18 -19 -20 -21 -22 -23 -24 -25 -26 -27 -28 -29 -30 -31 -32 -33 -34 -35 -36 -37 -38 -39 -40 -41 -42 -43 -44 -45 -46 -47 Volume1 1dB step (dB) 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 -16 -24 -16 -16 -16 -8 -16 0 Volume1 8dB step (dB) -8 Volume2 8dB step (dB) 0
15/22
TDA7468D
Table 12. VOLUME setting 2 (continua)
Target Volume (dB) -48 -49 -50 -51 -52 -53 -54 -55 -56 -57 -58 -59 -60 -61 -62 -63 -64 -65 -66 -67 -68 -69 -70 -71 -72 -73 -74 -75 -76 -77 -78 -79 -80 -81 -82 -83 -84 -85 -86 -87 Volume1 1dB step (dB) 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 0 -1 -2 -3 -4 -5 -6 -7 -56 -24 -48 -24 -40 -24 -32 -24 Volume1 8dB step (dB) -24 Volume2 8dB step (dB) -24
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TDA7468D
Table 13. TREBLE & BASS SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 TREBLE -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 14dB 12dB 10dB 8dB 6dB 4dB 2dB 0dB BASS (*) -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 14dB 12dB 10dB 8dB 6dB 4dB 2dB 0dB
(*) When BASS is programmed in the range -14dB/0dB, ALC is automatically switched to "OFF".
Table 14. OUTPUT
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 0 1 MUTE ON OFF
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TDA7468D
Table 15. BASS ALC
MSB D7 D6 D5 D4 D3 D2 D1 LSB D0 ALC Mode 1 0 ON OFF Detector 1 0 ON OFF Release Current Circuit 1 0 ON OFF Attack Time Resistor 0 0 1 1 0 1 0 1 12.5K 25K 50K 100K Threshold 0 0 1 1 0 1 0 1 700mVrms 485mVrms 320mVrms 170mVrms Attack Mode 0 1 MODE 1: Fixed Resistor MODE 2: Adaptive BASS ALC
Figure 9. BASS ALC : Threshold curve
VO (VRMS) Supply Voltage : 9.0V Frequency : 60Hz Bassfilter : 60Hz/28dB boost Internal release circuit : ON Attack mode : 12.5kohm, mode2(adaptive)
Threshold1
D00AU1100
Figure 10. BASS ALC : THD
THD [%] 10
Supply Voltage : 9.0V Frequency : 60Hz Bassfilter : 60Hz/28dB boost Internal release circuit : ON Attack mode : 12.5kohm, mode2(adaptive)
D99AU1101A
1
1
Threshold2
0.1
Threshold
Threshold
Threshold3
4
3
Thresh old2
Threshold4
0.01
0.1
0.001
0.01
0.1
1
VIN(VRMS)
0.01
Thresh
old1
0.1
1
VIN(VRMS)
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TDA7468D
8
IC1
Figure 15. PINS: BASSI_L, BASSI_R
VS
20A
Figure 11. PINS: IN1_L, IN1_R, IN2_L, IN2_R, IN3_L, IN3_R, IN4_L, IN4 _R, IS_L, IS_R, MIC
VS 20A
GND
45K
50K GND Vref
D99AU1092
BASSO-L,BASSO-R
D99AU1096
Figure 16. PINS: BASSO_L, BASSO_R Figure 12. PINS: OUT_L, OUT_R, IMUX_L, MUX_R
VS 20A 10
45K VS
20A
GND BASSI-L,BASSI-R
D99AU1097
GND
D99AU1093
Figure 17. PIN: ALC
VS
20A
Figure 13. PINS: TREBLE_L, TREBLE_R
VS
20A
100K
GND
D99AU1098
25K
GND
D99AU1094
Figure 18. PIN: CREF
VS 20A 25K
Figure 14. PINS: SCL, SDA
VS 20A
25K
GND
D99AU1099
GND
D99AU1095
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TDA7468D
Figure 19. SO20 Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 B C D (1) E e H h L k ddd 10.0 0.25 0.40 2.35 0.10 0.33 0.23 12.60 7.40 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.30 0.51 0.32 13.00 7.60 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 TYP. MAX. 0.104 0.012 0.200 0.013 0.512 0.299 inch
OUTLINE AND MECHANICAL DATA
0 (min.), 8 (max.) 0.10 0.004
(1) "D" dimension does not include mold flash, protusions or gate burrs. Mold flash, protusions or gate burrs shall not exceed 0.15mm per side.
SO20
0016022 D
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TDA7468D
Table 16. Revision History
Date January 2004 June 2004 Revision 2 3 Description of Changes First Issue in EDOCS DMS Changed the Style-sheet in compliance to the new "Corporate Technical Pubblications Design Guide"
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TDA7468D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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